1. Field of the Invention
This invention is related to the field of microprocessors, and more particularly, the mapping of physical register names to logical register name via a mapper circuit.
2. Description of the Related Art
High performance microprocessors use various techniques to speed up the execution of instructions, including the speculative/out-of-order execution of instructions. Since speculatively executed instructions may update the registers in a microprocessor, a means for storing speculative results that may be written to the logical (architected) registers may be implemented.
Register renaming is a technique used to keep track of speculative results that may be intended to be written to the logical registers. A microprocessor employing register renaming may include a physical register file which may store several copies of results intended for the logical registers. Each logical register may be associated with speculative results stored in a number of physical registers, as well as one non-speculative result stored in a physical register. This may allow several speculative results to be stored for each logical register, and may further allow for instructions to be executed out of order without concern for overwriting various results before they are no longer needed.
A mapper may provide associations between physical registers and logical registers. The mapper may provide associations for each logical register to a number of physical registers. These associations may include a non-speculative logical register state as well as several speculative logical register states. In general, the mapper may store a currently active logical-to-physical register association at a time T as well as several speculative logical-to-physical register associations for speculative results generated from a previous time U.
At times, some or all of the speculative register results generated between time T and time U may not be used. For example, speculative register results may include results generated from the prediction of a branch in a stream of instructions. If the branch is not taken, those results generated for instructions following the branch may not be used. In such cases, the mapper may be required to discard some or all of the speculative mappings made between time T and time U and reset itself to a state it was in at a previous point between time T and time U. In some cases, it may be necessary to back up the mapper to reflect a state resulting from retiring only a subset of operations of a particular instruction having multiple operations (i.e. a ‘partial retire’).